This invention relates to a high-current power transistor and more particularly to an integrated circuit that includes a high-current transistor.
The current gain of a bipolar transistor is a function of the current density in the base region, the gain increasing as the current density increases from zero, reaching a maximum and then decreasing as the current density continues to increase. In a typical planar integrated transistor wherein the emitter is usually orders of magnitude more wide at the substrate surface than its depth into the substrate, there is a pronounced tendency for the base current to concentrate at the periphery of the base-emitter junction. Thus the peripheral area of the base-emitter junction predominantly determines the maximum useful current carrying capacity of the transistor. The well known multi-emitter overlay power transistor configuration accounts for this phenomenon and provides a power transistor requiring less silicon substrate real-estate than the single emitter counterpart planar transistor. Another high current planar transistor, also following this rationale, employs a large centrally located emitter region that has a plurality of radially extending fingers that are interdigitated with inwardly extending fingers of the collector region at the substrate surface. The base region has an elongated serpentine area at the substrate surface that is interposed between the emitter and the collector to maximize the peripheral area of the base emitter junction.
It is an object of the present invention to provide a high current power transistor that may be readily incorporated in an integrated circuit and which transistor has a high ratio of rated current to substrate area.